1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device, and thus-manufactured semiconductor device.
2. Related Art
Recent VLSI is configured to contain several types of transistors differing in the thickness of gate insulating film. In general, a thin gate insulating film is adopted to the transistors composing a logic section, and a thick gate insulating film is adopted to the transistors composing a peripheral circuit. Characteristics of the individual transistors, such as the individual threshold voltages, are generally adjusted by introducing different doses of an impurity into the channels of the individual transistors. Introduction of an impurity into the channels generally follows the procedures below. All portions, but excluding the transistor aimed at implantation, are covered with a resist, an impurity is implanted, and the resist is then removed. For example, if there are three types of transistors varied in the thickness of gate insulating film in a circuit, the impurity implantation process is repeated three times.
Japanese Laid-Open Patent Publication No. 2006-93670 describes a configuration which is adjustable in the threshold voltage values simply by implanting an impurity into the conventional channel regions, and allows a metal, such as Hf, to reside between the gate insulating film and a Si-containing gate electrode. According to the description, the threshold voltage values of the transistors may be adjustable under a reduced dose of impurity.
Japanese Laid-Open Patent Publication No. 2007-165627 describes a technique of implanting fluorine right under each gate electrode of PMOS, in order to prevent NBTI (Negative Bias Temperature Instability), which is a degradation possibly occurs when each gate of the PMOS transistor is applied with a negative bias. According to the publication, the gate electrodes are formed, and fluorine ion is implanted using the gate electrodes as a mask so as to form a fluorine-implanted layer in a substrate, and the substrate is then annealed to thereby form a fluorine-diffused layer right under the gate electrodes. The publication describes a configuration in which the concentration of the fluorine-implanted layer in peripheral transistors having longer gate length is made higher than concentration of the fluorine-implanted layer in internal transistors having shorter gate length. According to the description, the configuration is contributive to improve NBTI, and is effective for the peripheral circuit where NBTI is more likely to occur.
Japanese Laid-Open Patent Publication No. 2006-344634 describes a technique of implanting fluorine into gate insulating film, for the purpose of suppressing degradation in the NBTI life time. According to the technique, fluorine ion is selectively implanted only into a PMOS transistor-forming region of a semiconductor substrate, and a gate insulating film is formed in each of the PMOS transistor-forming region and an NMOS transistor-forming region by annealing. Accordingly, in the PMOS transistor-forming region, fluorine diffuses from the substrate to the gate insulating film. The publication describes that the fluorine concentration becomes high at the interface between the gate electrode and the gate insulating film.
Japanese Laid-Open Patent Publication No. 2007-19191 describes a technique of forming a capacitor-forming trench in a substrate, an insulating film is formed thereon, and fluorine is then introduced by ion implantation into the substrate while using the insulating film as a through-film. Accordingly, fluorine may be introduced much more in the surficial portion of the substrate and bottom portion of the trench, while suppressing fluorine from being introduced into the side face of the capacitor-forming trench. According to the description, the implantation of fluorine may be contributive to exert an effect of accelerated oxidation on the bottom portion, so that the insulating film may be prevented from being grown unnecessarily thick on the side face, and so that the thickness of the film may be made uniform.
M. Inoue describes, in “Fluorine Incorporation into HfSiON Dielectric for Vth Control and Its Impact on Reliability for Poly-Si Gate PFET”, IEDM Technical Digest, October 2005, p. 413, that fluorine implanted before a gate insulating film (HfSiON) is formed finally resides in the gate insulating film.
The present inventor has recognized as follows. Conventional techniques have suffered from a large number of process steps, because different types of transistors needed independent ion implantation processes. Even with the technique described in Japanese Laid-Open Patent Publication No. 2006-93670, implantation of Hf or other metal may shift the threshold voltage of all transistors at a time, making it impossible to independently adjust the threshold voltage of the individual transistors. A plurality of times of fluorine implantation is still necessary even in the techniques described in Japanese Laid-Open Patent Publication Nos. 2007-165627 and 2006-344634.